ARM Cortex-M0 User Manual

Debug
6-2 Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
6.1 About debug
The processor implementation determines the debug configuration, including whether
debug is implemented. If debug is not implemented, no ROM table is present and the
halt, breakpoint, and watchpoint functionality is not present.
Basic debug functionality includes processor halt, single-step, processor core register
access, Reset and HardFault Vector Catch, unlimited software breakpoints, and full
system memory access. See the ARMv6-M ARM for more information.
The debug option might include either or both:
• a breakpoint unit supporting 1, 2, 3, or 4 hardware breakpoints
• a watchpoint unit supporting 1 or 2 watchpoints.
The processor implementation can be partitioned to place the debug components in a
separate power domain from the processor core and NVIC.
When debug is implemented, ARM recommend that a debugger identifies and connects
to the debug components using the CoreSight debug infrastructure.
Figure 6-1 on page 6-3 shows the recommended flow that a debugger can follow to
discover the components in the CoreSight debug infrastructure. In this case a debugger
reads the peripheral and component ID registers for each CoreSight component in the
CoreSight system.

ARM Cortex-M0 Specifications

General

Architecture	ARMv6-M
Data Bus Width	32-bit
Clock Speed	Up to 50 MHz
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Number of Cores	1
Memory Protection	Optional Memory Protection Unit (MPU)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Pipeline	3-stage
Max Clock Speed	50 MHz
Instruction Set	Thumb
Power Consumption	Low power design
Debug	Serial Wire Debug (SWD)
Die Size	Implementation dependent