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General| Data Width | 32-bit |
|---|---|
| Cores | 1 |
| MIPS per MHz | 0.9 |
| On-chip Debug | Yes |
| Instruction Set | ARM |
| Pipeline Stages | 3 |
| Operating Voltage | Implementation dependent |
| Manufacturing Process | Implementation dependent |
Describes the ARM7TDMI core as part of the ARM family of general-purpose 32-bit microprocessors.
Describes the ARM7TDMI processor's architecture, including ARM and Thumb instruction sets.
Illustrates the ARM7TDMI processor architecture, core, and functional diagrams with figures.
Provides a description of the ARM and Thumb instruction sets used on the ARM7TDMI processor.
Introduces the ARM7TDMI core's programmer's model, implementing ARMv4T architecture.
Describes the ARM and Thumb operating states and how to switch between them.
Explains how the ARM7TDMI processor views memory and its bi-endian capability (Little-endian, Big-endian).
Defines supported data types (words, halfwords, bytes) and their alignment requirements.
Lists and describes the ARM7TDMI processor's seven operating modes.
Details the ARM7TDMI processor's register set, including general-purpose, status, and banked registers.
Describes the CPSR and SPSRs, their arrangement, condition code flags, and control bits.
Explains exception handling mechanisms, entry/exit summaries, and different exception types.
Describes calculations for maximum and minimum interrupt latencies for FIQ and IRQ.
Details the ARM7TDMI processor's reset sequence after power-up and the behavior upon reset.
Describes the ARM7TDMI processor's Von Neumann architecture and single 32-bit data bus.
Groups ARM7TDMI processor bus interface signals into categories: clock, address, memory request, data.
Explains the four types of bus cycles: nonsequential, sequential, internal, and coprocessor transfer.
Describes address class signals like A[31:0], nRW, MAS[1:0], nOPC, nTRANS, LOCK, TBIT.
Details address bus timing configurations (pipelined, depipelined) and signal behavior.
Describes data bus signals (D[31:0], DIN, DOUT), ABORT, and byte latch enables.
Explains methods for stretching access times using MCLK modulation or nWAIT.
Discusses using nTRANS and nM[4:0] to distinguish between User and privileged mode accesses.
Details the sequence of events when the ARM7TDMI processor is reset after power-up.
Explains how coprocessors extend ARM7TDMI functionality with specialized instructions.
Lists signals used to interface the ARM7TDMI core to a coprocessor, grouped by category.
Describes signals that allow coprocessors to track instructions in the ARM7TDMI processor pipeline.
Details the handshake signals (nCPI, CPA, CPB) used between the ARM7TDMI core and coprocessors.
Explains how to connect single and multiple coprocessors to the ARM7TDMI processor system.
Provides guidance on handling systems without external coprocessors, including signal tying.
Explains how the processor handles undefined instructions and the role of coprocessors.
Describes how the nTRANS signal enables privileged access to coprocessor instructions.
Details the ARM7TDMI processor's debug interface based on IEEE Std. 1149.1.
Describes the typical components of a debug system: debug host, protocol converter, and debug target.
Introduces primary external signals for the debug interface: BREAKPT, DBGRQ, DBGACK.
Explains clock switching between MCLK and DCLK during debug and test operations.
Explains how to determine the processor's state (ARM or Thumb) when entering debug mode.
Describes the EmbeddedICE-RT logic for integrated on-chip debug support, including watchpoints and registers.
Explains how to disable the EmbeddedICE-RT logic using the DBGEN signal for power saving.
Describes the Debug Communications Channel (DCC) for passing information between target and host debugger.
Explains conventions used in instruction cycle timing tables, including signal pipeline and notation.
Details the cycle timings for ARM branch and branch with link instructions.
Details the cycle timings for Thumb branch with link operations.
Details the cycle timings for the Branch and Exchange (BX) operation.
Describes the execution cycle for data operation instructions, including shift operations.
Details cycle timings for multiply and multiply accumulate instructions.
Describes the cycle timings for the Load Register (LDR) instruction.
Describes the cycle timings for the Store Register (STR) instruction.
Details the cycle timings for Load Multiple Registers (LDM) instructions.
Details the cycle timings for Store Multiple Registers (STM) instructions.
Describes the cycle timings for the Data Swap (SWP) instruction.
Details cycle timings for software interrupts and exception entry.
Describes the cycle timings for coprocessor data operation instructions.
Details cycle timings for coprocessor data transfer from memory to coprocessor.
Details cycle timings for coprocessor data transfer from coprocessor to memory.
Details cycle timings for coprocessor register transfer, load from coprocessor.
Lists and describes AC timing diagrams for various interface signals and operations.
Provides notes and alphabetical listing of AC timing parameters used in the chapter.
Refers users to suppliers for information on operating conditions and maximum ratings.
Shows dimensions of output drivers for a 0.18µm ARM7TDMI r4p1 processor.
Lists and describes the different types of signals used in the ARM7TDMI r4p1 processor.
Provides detailed descriptions for all signals used by the ARM7TDMI r4p1 processor.
Explains the three JTAG-style scan chains enabling debugging and configuration of EmbeddedICE-RT logic.
Describes how to reset the Test Access Port (TAP) controller into its correct state after power-up.
Discusses the requirement for driving test interface inputs to good logic levels due to lack of internal pullups.
Describes the 4-bit instruction register, its capture value, and scan order.
Lists and describes the public instructions used with the TAP controller for JTAG operations.
Describes the seven test data registers that connect between TDI and TDO for scan testing.
Explains the memory clock (MCLK) and internal debug clock (DCLK) and their switching during debug.
Explains how to determine the processor's state (ARM or Thumb) when entering debug mode.
Details how the debugger tracks the program counter to branch back to interrupted program flow.
Covers priorities of exceptions relative to breakpoints and watchpoints.
Lists the signals and types for scan chain 0 cells, comprising the data bus and control signals.
Describes the two watchpoint units, their registers (address, data, control) and functions.
Explains how to program hardware and software breakpoints using watchpoint units.
Details how to program watchpoints for data accesses, including data-dependent and mode-specific criteria.
Describes the debug control register bits for enabling/disabling features and controlling behavior.
Summarizes key changes in ARM7TDMI Rev 4, including EmbeddedICE-RT and DCC improvements.
Provides detailed descriptions of changes in ARM7TDMI Rev 4, such as EmbeddedICE-RT logic additions.
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