ARM ARM7TDMI - Figure 4-2 Coprocessor Register Transfer Sequence

To Next Page

To Previous Page

Coprocessor Interface

Caution

It is essential that any action taken by the coprocessor while it is busy-waiting is

idempotent. This means that the actions taken by the coprocessor must not corrupt the

state of the coprocessor, and must be repeatable with identical results. The coprocessor

can only change its own state when the instruction has been executed.

The ARM7TDMI processor usually returns from processing the interrupt to retry the

coprocessor instruction. Other coprocessor instructions can be executed before the

interrupted instruction is executed again.

4.4.5 Coprocessor register transfer instructions

The coprocessor register transfer instructions, MCR and MRC, are used to transfer data

between a register in the ARM7TDMI processor register bank and a register in the

coprocessor register bank. An example sequence for a coprocessor register transfer is

shown in Figure 4-2.

Figure 4-2 Coprocessor register transfer sequence

ADD SUB MCR TST

ADD SUB MCR SUB

ADD SUB TST SUB

MCLK

Fetch stage

Decode stage

Execute stage

nCPI

CPA

CPB

SUB

TST

MCR

ADD SUB MCR TST SUB DATA INSTR

D[31:0]

Other manuals for ARM ARM7TDMI