ARM ARM7TDMI - Table 4-3 Summary of Coprocessor Signaling

Coprocessor Interface
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4.4.2 The ARM7TDMI processor
Coprocessor instructions progress down the ARM7TDMI core pipeline in step with the
coprocessor pipeline. A coprocessor instruction is executed if the following are true:
1. The coprocessor instruction has reached the Execute stage of the pipeline. It
might not if it is preceded by a branch.
2. The ARM7TDMI processor cannot execute the instruction because the
instruction is in the coprocessor or undefined part of the instruction set.
3. The instruction has passed its conditional execution tests.
If all these requirements are met, the ARM7TDMI core signals by taking nCPI LOW,
this commits the coprocessor to the execution of the coprocessor instruction.
4.4.3 Coprocessor signaling
The coprocessor responses are listed in Table 4-3.
Table 4-3 Summary of coprocessor signaling
CPA CPB Response Remarks
0 0 Coprocessor present If a coprocessor can accept an instruction, and can start that instruction
immediately, it must signal this by driving both CPA and CPB LOW. The
ARM7TDMI processor then ignores the coprocessor instruction and
executes the next instruction as normal.
0 1 Coprocessor busy If a coprocessor can accept an instruction, but is currently unable to process
that request, it can stall the ARM7TDMI processor by asserting busy-wait.
This is signaled by driving CPA LOW, but leaving CPB HIGH. When the
coprocessor is ready to start executing the instruction it signals this by
driving CPB LOW. This is shown in Figure 4-1 on page 4-8.
1 0 Invalid response -
1 1 Coprocessor absent If a coprocessor cannot accept the instruction currently in Decode, it must
leave CPA and CPB both HIGH. The ARM7TDMI processor takes the
undefined instruction trap.