ARM ARM7TDMI - Figure 3-18 Memory Access

Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-25
Because two memory cycles are required, nWAIT is used to stretch the internal
processor clock. nWAIT does not affect the operation of the data latches. Using this
method, data can be taken from memory a word, halfword, or byte at a time and the
memory can have as many wait states as required. In multi-cycle memory accesses,
nWAIT must be held LOW until the final part is latched.
In the example shown in Figure 3-18, the BL[3:0] signals are driven to value
0x3 in the
first cycle so that only the latches on D[15:0] are open. BL[3:0] can be driven to value
0xF and all of the latches opened. This does not affect the operation of the core because
the latches on D[31:16] are written with the correct data during the second cycle.
Note
BL[3:0] must be held HIGH during store cycles.
Figure 3-18 Memory access
Figure 3-19 on page 3-26 shows a halfword load from single-wait state byte-wide
memory. In the figure, each memory access takes two cycles:
• In the first access:
— BL[3:0] are driven to
0xF
— the correct data is latched from D[7:0]
— unknown data is latched from D[31:8].
• In the second cycle, the byte for D[15:8] is latched so the halfword on D[15:0] is
correctly read from memory. It does not matter that D[31:16] are unknown
because the core extracts only the halfword of interest.
MCLK
APE
nMREQ
SEQ
A[31:0]
nWAIT
D[15:0]
D[31:16]
BL[3:0] 0x3 0xC