ARM ARM7TDMI - About EmbeddedICE-RT Logic

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Debug Interface

5.6 About EmbeddedICE-RT logic

The EmbeddedICE-RT logic provides integrated on-chip debug support for the

ARM7TDMI core.

The EmbeddedICE-RT logic is programmed serially using the ARM7TDMI processor

TAP controller. Figure 5-5 illustrates the relationship between the core, the

EmbeddedICE-RT logic, and the TAP controller, showing only the pertinent signals.

Figure 5-5 ARM7 CPU main processor logic, TAP controller, and EmbeddedICE-RT logic

The EmbeddedICE-RT logic comprises:

• two real-time watchpoint units

• three independent registers:

— debug control register

nOPC

ARM CPU main

processor logic

DBGRQI

A[31:0]

D[31:0]

nRW

TBIT

MAS[1:0]

nTRANS

DBGACKI

BREAKPTI

IFEN

ECLK

nMREQ

EmbeddedICE-RT

Logic

RANGEOUT1

DBGACK

BREAKPT

RANGEOUT0

EXTERN0

DBGRQ

EXTERN1

DBGEN

DBGRQI

TAP

TCK

TMS

TDI

TDO

nTRST

SDOUT CONTROLSDIN

Main Page

Preface16
Chapter 1 Introduction22
Chapter 2 Programmer's Model48
Chapter 3 Memory Interface72
Chapter 4 Coprocessor Interface104
Chapter 5 Debug Interface122
Chapter 6 Instruction Cycle Timings145
Chapter 7 Ac and DC Parameters173
Appendix A Signal and Transistor Descriptions200
Appendix B Debug in Depth211
Appendix C271
- Differences between Rev 3A and Rev271
Appendix C Differences between Rev 3A and Rev272
- Summary of Differences between Rev 3A and Rev 4272
- Detailed Descriptions of Differences between Rev 3A and Rev 4273
Glossary277

ARM ARM7TDMI - About EmbeddedICE-RT Logic

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