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ARM ARM7TDMI - Priorities and Exceptions

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Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-33
B.10 Priorities and exceptions
When a breakpoint or a debug request occurs, the normal flow of the program is
interrupted. Debug can be treated as another type of exception. The interaction of the
debugger with other exceptions is described in Behavior of the program counter in
debug state on page B-30. This section covers the following priorities:
Breakpoint with Prefetch Abort
Interrupts
Data Aborts on page B-34.
B.10.1 Breakpoint with Prefetch Abort
When a breakpointed instruction fetch causes a Prefetch Abort, the abort is taken and
the breakpoint is disregarded. Usually, Prefetch Aborts occur when, for example, an
access is made to a virtual address that does not physically exist and the returned data
is therefore invalid. In such a case, the normal action of the operating system is to swap
in the page of memory and to return to the previously-invalid address. This time, when
the instruction is fetched and providing the breakpoint is activated, it can be
data-dependent, the ARM7TDMI core enters debug state.
The Prefetch Abort, therefore, takes higher priority than the breakpoint.
B.10.2 Interrupts
When the ARM7TDMI core enters halt debug state, interrupts are automatically
disabled.
If an interrupt is pending during the instruction prior to entering debug state, the
ARM7TDMI core enters debug state in the mode of the interrupt. On entry to debug
state, the debugger cannot assume that the ARM7TDMI core is in the mode expected
by the user program. The debugger must check the PC, the CPSR, and the SPSR to
accurately determine the reason for the exception.
Debug, therefore, takes higher priority than the interrupt, but the ARM7TDMI core
does remember that an interrupt has occurred.
If bit [4], monitor mode enable, of the Debug control register is set, FIQs remain
enabled. An entry to the abort exception routine disables IRQs, so in monitor mode the
abort exception routine must re-enable IRQs before they can be recognized and
serviced.

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