Debug Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-7
5.3 Debug interface signals
There are three primary external signals associated with the debug interface:
• BREAKPT and DBGRQ are system requests for the processor to enter debug
state
• DBGACK is used to indicate that the core is in debug state.
Note
DBGEN must be configured HIGH to fully enable the debug features of the
processor. See Disabling EmbeddedICE-RT on page 5-16.
The following sections describe:
• Entry into debug state
• Action of the ARM7TDMI processor in debug state on page 5-10.
5.3.1 Entry into debug state
The ARM7TDMI processor is forced into debug state following a breakpoint,
watchpoint, or debug request.
In monitor mode, the processor continues to execute instructions in real time, and will
take an abort exception. The abort status register enables you to establish whether the
exception was because of a breakpoint or watchpoint, or to a genuine memory abort.
You can use the EmbeddedICE-RT logic to program the conditions under which a
breakpoint or watchpoint can occur. Alternatively, you can use the BREAKPT signal
to enable external logic to flag breakpoints or watchpoints and monitor the following:
• address bus
• data bus
• control signals.
The timing is the same for externally-generated breakpoints and watchpoints. Data must
always be valid on the falling edge of MCLK. When this is an instruction to be
breakpointed, the BREAKPT signal must be HIGH on the next rising edge of MCLK.
Similarly, when the data is for a load or store, asserting BREAKPT on the rising edge
of MCLK marks the data as watchpointed.
When the processor enters debug state, the DBGACK signal is asserted. The timing for
an externally-generated breakpoint is shown in Figure 5-3 on page 5-8.
The following sections describe:
• Entry into debug state on breakpoint on page 5-8
• Entry into debug state on watchpoint on page 5-9
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