Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-17
3.6 Data timed signals
This section describes:
• D[31:0], DOUT[31:0], and DIN[31:0]
• ABORT on page 3-24
• Byte latch enables on page 3-24
• Byte and halfword accesses on page 3-26.
3.6.1 D[31:0], DOUT[31:0], and DIN[31:0]
The ARM7TDMI processor provides both unidirectional data buses, DIN[31:0],
DOUT[31:0], and a bidirectional data bus, D[31:0]. The configuration input BUSEN is
used to select which is active. Figure 3-11 shows the arrangement of the data buses and
bus-splitter logic.
Figure 3-11 External bus arrangement
When the bidirectional data bus is being used then you must disable the unidirectional
buses by driving BUSEN LOW. The timing of the bus for three cycles, load-store-load,
is shown in Figure 3-12 on page 3-18.
ARM7TDMI
EmbeddICE
Logic
Latch
DOUT[31:0]
D[31:0]
DIN[31:0]
G
Latch control
Buffer control
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