Signal and Transistor Descriptions
A-4 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
A.3 Signal descriptions
Table A-3 describes all the signals used for the ARM7TDMI r4p1 processor.
Table A-3 Signal descriptions
Name Type Description
A[31:0]
Addresses
O This is the 32-bit address bus. ALE, ABE, and APE are used to control
when the address bus is valid.
ABE
Address bus enable
IC The address bus drivers are disabled when this is LOW, putting the address
bus into a high impedance state. This also controls the LOCK, MAS[1:0],
nRW, nOPC, and nTRANS signals in the same way. ABE must be tied
HIGH if there is no system requirement to disable the address drivers.
ABORT
Memory abort
IC The memory system uses this signal to tell the processor that a requested
access is not allowed.
ALE
Address latch enable
IC This signal is provided for backwards compatibility with older ARM
processors. For new designs, if address retiming is required, ARM Limited
recommends the use of APE, and for ALE to be connected HIGH.
The address bus, LOCK, MAS[1:0], nRW, nOPC, and nTRANS signals
are latched when this is held LOW. This enables these address signals to be
held valid for the complete duration of a memory access cycle. For example,
when interfacing to ROM, the address must be valid until after the data has
been read.
APE
Address pipeline enable
IC Selects whether the address bus, LOCK, MAS[1:0], nRW, nTRANS, and
nOPC signals operate in pipelined (APE is HIGH) or depipelined mode
(APE is LOW).
Pipelined mode is particularly useful for DRAM systems, where it is
desirable to provide the address to the memory as early as possible, to allow
longer periods for address decoding and the generation of DRAM control
signals. In this mode, the address bus does not remain valid to the end of the
memory cycle.
Depipelined mode can be useful for SRAM and ROM access. Here the
address bus, LOCK, MAS[1:0], nRW, nTRANS, and nOPC signals must
be kept stable throughout the complete memory cycle. However, this does
not provide optimum performance.
See Address timing on page 3-14 for details of this timing.
BIGEND
Big endian configuration
IC Selects how the processor treats bytes in memory:
• HIGH for big-endian format
• LOW for little-endian format.
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