ARM ARM7TDMI - Figure 3-6 Coprocessor Register Transfer Cycles

Memory Interface
3-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-6 Coprocessor register transfer cycles
3.3.6 Summary of ARM memory cycle timing
A summary of ARM7TDMI processor memory cycle timing is shown in Figure 3-7.
Figure 3-7 Memory cycle timing
MCLK
A[31:0]
nMREQ
SEQ
D[31:0]
Memory Memory Coprocessor
N-cycle
C-cycle
C-cycleI-cycleS-cycle
a+8a+4a
MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
N-cycle