Memory Interface
3-12 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
The address produced by the processor is always a byte address. However, the memory
system must ignore the bottom redundant bits of the address. The significant address
bits are listed in Table 3-3.
The size of transfer does not change during a burst of S-cycles.
The ARM7TDMI processor cannot generate bursts of byte transfers.
Note
During instruction accesses the redundant address bits are undefined. The memory
system must ignore these redundant bits.
A writable memory system for the ARM7TDMI processor must have individual byte
write enables. Both the C Compiler and the ARM debug tool chain, for example,
Multi-ICE, assume that arbitrary bytes in the memory can be written. If individual byte
write capability is not provided, you might not be able to use either of these tools
without data corruption.
3.4.4 nOPC
The nOPC output conveys information about the transfer. An MMU can use this signal
to determine whether an access is an opcode fetch or a data transfer. This signal can be
used with nTRANS to implement an access permission scheme. The meaning of nOPC
is listed in Table 3-4.
Table 3-3 Significant address bits
MAS[1:0] Width Significant address bits
00 Byte A[31:0]
01 Halfword A[31:1]
10 Word A[31:2]
11 Reserved -
Table 3-4 nOPC
nOPC Opcode/data
0 Opcode
1Data
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