ARM ARM7TDMI User Manual

Instruction Cycle Timings
6-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
m+1 pc+12 0 2 - 1 0 1
m+2 pc+12 0 2 - 0 1 1
pc+12
Table 6-7 Multiply long instruction cycle operations
Cycle Address nRW MAS[1:0] Data nMREQ SEQ nOPC
1 pc+8 0 i (pc+8) 1 0 0
2pc+120i - 1 01
•pc+120i - 1 01
mpc+120i - 1 01
m+1 pc+12 0 i - 1 0 1
m+2 pc+12 0 i - 0 1 1
pc+12
Table 6-8 Multiply accumulate long instruction cycle operations
Cycle Address nRW MAS[1:0] Data nMREQ SEQ nOPC
1 pc+8 0 2 (pc+8) 1 0 0
2pc+802 - 1 01
•pc+1202 - 1 01
mpc+1202 - 1 01
m+1 pc+12 0 2 - 1 0 1
m+2 pc+12 0 2 - 1 0 1
m+3 pc+12 0 2 - 0 1 1
pc+12
Table 6-6 Multiply accumulate instruction cycle operations (continued)
Cycle Address nRW MAS[1:0] Data nMREQ SEQ nOPC

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English