ARM ARM7TDMI - Figure 3-5 Merged IS Cycle

Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-9
Figure 3-5 Merged IS cycle
Note
When designing a memory controller, ensure that the design also works when an I-cycle
is followed by an N-cycle to a different address. This sequence can occur during
exceptions, or during writes to the PC. It is essential that the memory controller does
not commit to the memory cycle during an I-cycle.
3.3.5 Coprocessor register transfer cycles
During a coprocessor register transfer cycle, the ARM7TDMI processor uses the data
buses to transfer data to or from a coprocessor. A memory cycle is not required and the
memory controller does not initiate a transaction. The memory system must not drive
onto the data bus during a coprocessor register transfer cycle.
The coprocessor interface is described in Chapter 4 Coprocessor Interface. The
coprocessor register transfer cycle is shown in Figure 3-6 on page 3-10.
MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
I-cycle S-cycle