Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-11
3.4 Addressing signals
The address class signals are:
• A[31:0]
• nRW
• MAS[1:0]
• nOPC on page 3-12
• nTRANS on page 3-13
• LOCK on page 3-13
• TBIT on page 3-13.
3.4.1 A[31:0]
A[31:0] is the 32-bit address bus that specifies the address for the transfer. All addresses
are byte addresses, so a burst of word accesses results in the address bus incrementing
by four for each cycle.
The address bus provides 4GB of linear addressing space.
When a word access is signaled the memory system ignores the bottom two bits, A[1:0],
and when a halfword access is signaled the memory system ignores the bottom bit,
A[0].
All data values must be aligned on their natural boundaries. All words must be
word-aligned.
3.4.2 nRW
nRW specifies the direction of the transfer. nRW indicates an ARM7TDMI processor
write cycle when HIGH, and an ARM7TDMI processor read cycle when LOW. A burst
of S-cycles is always either a read burst, or a write burst. The direction cannot be
changed in the middle of a burst.
3.4.3 MAS[1:0]
The MAS[1:0] bus encodes the size of the transfer. The ARM7TDMI processor can
transfer word, halfword, and byte quantities.
All writable memory in an ARM7TDMI processor based system must support the
writing of individual bytes to enable the use of the C Compiler and the ARM debug tool
chain, for example Multi-ICE.
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