Instruction Cycle Timings
6-26 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
6.17 Coprocessor register transfer, store to coprocessor
This is the same as described in Coprocessor register transfer, load from coprocessor
on page 6-25, except that the last cycle is omitted.
The cycle timings are listed in Table 6-20 where:
• b represents the busy cycles.
Note
Coprocessor register transfer operations are not available in Thumb state.
Table 6-20 Coprocessor register transfer, store to coprocessor
Cycle Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB
ready 1 pc+8 2 0 (pc+8) 1 1 0 0 0 0
2pc+1221Rd0 01111
pc+12
not ready 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
2pc+820- 1 01001
•pc+820- 1 01001
bpc+820- 1 11000
b+1 pc+12 2 1 Rd 0 0 1 1 1 1
pc+12
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