Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-27
6.18 Undefined instructions and coprocessor absent
When the processor attempts to execute an instruction that neither it nor a coprocessor
can perform (including all undefined instructions) this causes the processor to take the
undefined instruction trap.
Cycle timings are listed in Table 6-21 where:
• C represents the current mode-dependent value
• T represents the current state-dependent value.
Note
• Coprocessor instructions are not available in Thumb state.
• CPA and CPB are HIGH during the undefined instruction trap.
Table 6-21 Undefined instruction cycle operations
Cycle Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI nTRANS Mode
TBI
T
1 pc+2L i 0 (pc+2L) 1 0 0 0 C Old T
2pc+2Li0- 0 001C OldT
3 Xn 2 0 (Xn) 0 1 0 1 1 00100 0
4 Xn+4 2 0 (Xn+4) 0 1 0 1 1 00100 0
Xn+8
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