ARM ARM7TDMI - The Abort Status Register; Figure B-12 Debug Abort Status Register

Debug in Depth
B-56 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
B.17 The abort status register
Only bit [0] of this 32-bit read/write register is used. It determines whether an abort
exception entry was caused by a breakpoint, a watchpoint, or a real abort. The format is
shown in Figure B-12.
Figure B-12 Debug abort status register
This bit is set when the ARM7TDMI core takes a prefetch or data abort as a result of a
breakpoint or watchpoint. If, on a particular instruction or data fetch, both the debug
abort and the external abort signal are asserted, then the external abort takes priority, and
the DbgAbt bit is not set. When set, DbgAbt remains set until reset by the user. The
register is accessed by
MRC and MCR instructions.
DbgAbt
0
SBZ/RAZ
31:1