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ARM ARM7TDMI - Key to Timing Diagram Conventions

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Preface
xviii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
monospace
italic
Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace
bold
Denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
The Opcode_2 value selects which register is accessed.
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

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