ARM ARM7TDMI User Manual

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-45
Figure B-8 Watchpoint control value and mask format
Bit [8] of the control value register is the ENABLE bit and cannot be masked.
The bits have the following functions:
nRW Compares against the write signal from the core to detect the
direction of bus activity. nRW is 0 for a read cycle and 1 for a
write cycle.
MAS[1:0] Compares against the MAS[1:0] signal from the core to detect the
size of bus activity.
The encoding is listed in Table B-6.
nOPC Detects if the current cycle is an instruction fetch, with nOPC=0,
or a data access, with nOPC=1.
nTRANS Compares against the not translate signal from the core to
distinguish between User Mode, with nTRANS=0, and non-user
mode, with nTRANS=1, accesses.
EXTERN[1:0] Is an external input to EmbeddedICE-RT that enables the
watchpoint to be dependent upon some external condition. The
EXTERN input for Watchpoint 0 is labeled EXTERN0. The
EXTERN input for Watchpoint 1 is labeled EXTERN1.
CHAIN Can be referred to the chain output of another watchpoint to
implement, for example, debugger requests of the form:
breakpoint on address YYY only when in process XXX . In the
ARM7TDMI core EmbeddedICE-RT logic, the CHAINOUT
ENABLE CHAINRANGE EXTERN nOPCnTRANS MAS[1] nRWMAS[0]
8 67 5 34 2 01
Table B-6 MAS[1:0] signal encoding
Bit [1] Bit [0] Data size
00Byte
01Halfword
10Word
1 1 Reserved

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English