Debug Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-11
5.4 ARM7TDMI core clock domains
The ARM7TDMI clocks are described in Clocks on page 5-3.
This section describes:
• Clock switch during debug
• Clock switch during test on page 5-12.
5.4.1 Clock switch during debug
When the ARM7TDMI processor enters halt debug state, it switches automatically
from MCLK to DCLK, it then asserts DBGACK in the HIGH phase of MCLK. The
switch between the two clocks occurs on the next falling edge of MCLK. This is shown
in Figure 5-4.
The core is forced to use DCLK as the primary clock until debugging is complete. On
exit from debug, the core must be allowed to synchronize back to MCLK. This must be
done by the debugger in the following sequence:
1. The final instruction of the debug sequence is shifted into the data bus scan chain
and clocked in by asserting DCLK.
2. RESTART is clocked into the TAP instruction register.
The core now automatically resynchronizes back to MCLK and starts fetching
instructions from memory at MCLK speed.
See Exit from debug state on page B-27.
Figure 5-4 Clock switching on entry to debug state
Note
In monitor mode, the core continues to be clocked by MCLK, and DCLK is not used.
MCLK
DBGACK
DCLK
ECLK
Multiplexer
switching point
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