Instruction Cycle Timings
6-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
6.8 Store register
The first cycle of a store register instruction is similar to the first cycle of load register
instruction. During the second cycle the base modification is performed, and at the same
time the data is written to memory. There is no third cycle.
The cycle timings are listed in Table 6-11 where:
• c represents the current processor mode:
—c=0 for User mode
— c=1 for all other modes
• d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times.
• s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Table 6-11 Store register instruction cycle operations
Cycle Address MAS[1:0] nRW Data nMREQ SEQ nOPC nTRANS
1 pc+2L i 0 (pc+2L) 0 0 0 c
2alu s 1Rd0 01d
pc+3L
To Next Page
Loading...
