Debug Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 5-17
5.8 Debug Communications Channel
The ARM7TDMI processor EmbeddedICE-RT logic contains a Debug
Communications Channel (DCC) to pass information between the target and the host
debugger. This is implemented as coprocessor 14 (CP14).
The DCC comprises:
• a 32-bit communications data read register
• a 32-bit communications data write register
• a 32-bit communications control register for synchronized handshaking between
the processor and the asynchronous debugger.
These registers are located in fixed locations in the EmbeddedICE-RT logic register
map, as shown in Figure B-7 on page B-43, and are accessed from the processor using
MCR
and
MRC
instructions to coprocessor 14.
The registers are accessed as follows:
By the debugger Through scan chain 2 in the usual way.
By the processor Through coprocessor register transfer instructions.
The following sections describe:
• DCC control register
• Communications through the DCC on page 5-18.
5.8.1 DCC control register
The DCC control register controls synchronized handshaking between the processor
and the debugger. The control register format is shown in Figure 5-6.
Figure 5-6 DCC control register format
31 30 29 28 27 2 1 0
Reserved
EmbeddedICE
version
Control
bits
DCC data read register
0 1 0 0 · · W R
DCC data write register
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