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Memory Interface

The macrocell has an additional bus control signal, nENIN that enables the external

system to manually tristate the bus. In the simplest systems, nENIN can be tied LOW

and nENOUT can be ignored. In many applications, when the external data bus is a

shared resource, greater control might be required. In this situation, nENIN can be used

to delay when the external bus is driven.

Note

For backwards compatibility, DBE is also included. At the macrocell level, DBE and

nENIN have almost identical functionality and in most applications one can be tied to

keep the data bus enabled.

The processor has another output control signal called TBE. This signal is usually only

used during test and must be tied HIGH when not in use. When driven LOW, TBE

forces all tristateable outputs to high impedance, it is as though both DBE and ABE

have been driven LOW, causing the data bus, the address bus, and all other signals

normally controlled by ABE to become high impedance.

Note

There is no scan cell on TBE. Therefore, TBE is completely independent of scan data

and can be used to put the outputs into a high impedance state while scan testing takes

place.

Table 3-6 lists the tristate control of the processor outputs.

Table 3-6 Tristate control of processor outputs

Processor output ABE DBE TBE

A[31:0] Yes - Yes

D[31:0] -YesYes

nRW Yes - Yes

LOCK Yes - Yes

MAS[1:0] Yes - Yes

nOPC Yes - Yes

nTRANS Yes - Ye s

Brand

Model

ARM7TDMI

ARM ARM7TDMI User Manual

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