ARM ARM7TDMI - Privileged Mode Access

Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-31
3.8 Privileged mode access
If only privileged mode access is required from a memory system, you are advised to
use the nTRANS pin on the core. This signal distinguishes between User and privileged
accesses.
This is recommended because if the Operating System (OS) accesses memory on behalf
of the current application, it must perform these accesses in User mode. This is achieved
using the
LDRT and STRT instructions that set nTRANS appropriately.
This measure avoids the possibility of a hacker deliberately passing an invalid pointer
to an OS and getting the OS to access this memory with privileged access. This
technique could otherwise be used by a hacker to enable the user application to access
any memory locations such as I/O space.
The least significant five bits of the CPSR are also output from the core as inverted
signals, nM[4:0]. These indicate the current processor mode as listed in Table 3-8.
Note
The only time to use the nM[4:0] signals is for diagnostic and debug purposes.
Table 3-8 Use of nM[4:0] to indicate current processor mode
M[4:0] nM[4:0] Mode
10000 01111 User
10001 01110 FIQ
10010 01101 IRQ
10011 01100 Supervisor
10111 01000 Abort
11011 00100 Undefined
11111 00000 System