ARM ARM7TDMI - Table 7-11 Exception Timing Parameters; Figure 7-11 Exception Timing

AC and DC Parameters
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-11
Figure 7-11 Exception timing
Note
In Figure 7-11, to guarantee recognition of the asynchronous interrupt (ISYNC=0) or
reset source, the appropriate signals must be setup or held as follows:
•setup T
is
and T
rs
respectively before the corresponding clock edge
• hold T
im
and T
is
respectively after the corresponding clock edge.
These inputs can be applied fully asynchronously where the exact cycle of recognition
is unimportant.
The timing parameters used in Figure 7-11 are listed in Table 7-11.
T
im
T
abth
T
rs
T
abts
T
is
T
rm
MCLK
ABORT
nFIQ
nIRQ
nRESET
Table 7-11 Exception timing parameters
Symbol Parameter
Parameter
type
T
abth
ABORT hold time from MCLKf Minimum
T
abts
ABORT set up time to MCLKf Minimum
T
im
Asynchronous interrupt guaranteed nonrecognition time, with ISYNC=0 Maximum
T
is
Asynchronous interrupt set up time to MCLKf for guaranteed recognition, with ISYNC=0 Minimum
T
rm
Reset guaranteed nonrecognition time Maximum
T
rs
Reset setup time to MCLKr for guaranteed recognition Minimum