ARM ARM7TDMI - Figure B-2 Test Access Port Controller State Transitions

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-5
Scan chain 2
Scan chain 2 enables access to the EmbeddedICE-RT logic registers. See Test data
registers on page B-14 for details.
B.1.2 TAP state machine
The process of serial test and debug is best explained in conjunction with the JTAG state
machine. Figure B-2 shows the state transitions that occur in the TAP controller.
Figure B-2 Test access port controller state transitions
From IEEE Std 1149.1-1990. Copyright 1999 IEEE. All rights reserved.
Test-Logic Reset
0xF
Run-Test/Idle
0xC
Select-DR-Scan
0x7
Capture-DR
0x6
Capture-IR
0xE
Shift-DR
0x2
Shift-IR
0xA
Exit1-DR
0x1
Exit1-IR
0x9
Pause-DR
0x3
Pause-IR
0xB
Exit2-DR
0x0
Exit2-IR
0x8
Update-DR
0x5
Update-IR
0xD
Select-IR-Scan
0x4
tms=1
tms=0
tms=0
tms=1 tms=1 tms=1
tms=0
tms=0
tms=1
tms=0
tms=1
tms=1tms=1
tms=0 tms=0
tms=1 tms=1
tms=1
tms=0
tms=1
tms=0
tms=0
tms=1
tms=0
tms=1
tms=1
tms=0
tms=1
tms=0
tms=0
tms=0
tms=0