ARM ARM7TDMI - Figure 2-4 Register Organization in Thumb State

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Programmer’s Model

2.6.2 The Thumb-state register set

The Thumb-state register set is a subset of the ARM-state set. The programmer has

access to:

• 8 general registers, r0–r7

•the PC

•the SP

•the LR

• the CPSR.

There are banked SPs, LRs, and SPSRs for each privileged mode. This register set is

shown in Figure 2-4.

Figure 2-4 Register organization in Thumb state

Thumb-state general registers and program counter

System and User

CPSR CPSR

SPSR_fiq

CPSR

SPSR_svc

CPSR

SPSR_abt

CPSR

SPSR_irq

CPSR

SPSR_und

Thumb-state program status registers

= banked register

FIQ

SP_fiq

LR_fiq

Supervisor

SP_svc

LR_svc

Abort

SP_abt

LR_abt

IRQ

SP_irq

LR_irq

Undefined

SP_und

LR_und

Main Page

Preface16
Chapter 1 Introduction22
Chapter 2 Programmer's Model48
Chapter 3 Memory Interface72
Chapter 4 Coprocessor Interface104
Chapter 5 Debug Interface122
Chapter 6 Instruction Cycle Timings145
Chapter 7 Ac and DC Parameters173
Appendix A Signal and Transistor Descriptions200
Appendix B Debug in Depth211
Appendix C271
- Differences between Rev 3A and Rev271
Appendix C Differences between Rev 3A and Rev272
- Summary of Differences between Rev 3A and Rev 4272
- Detailed Descriptions of Differences between Rev 3A and Rev 4273
Glossary277

ARM ARM7TDMI - Figure 2-4 Register Organization in Thumb State

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