ARM ARM7TDMI - Figure 3-15 Data Write Bus Cycle; Figure 3-16 Data Bus Control Circuit

Memory Interface
3-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-15 Data write bus cycle
Figure 3-16 Data bus control circuit
MCLK
A[31:0]
nRW
nENOUT
D[31:0]
memory cycle
Scan
cell
Scan
cell
Scan
cell
Data direction
control from core
DBE
nENOUT
nENIN
TBE
D[31:0]
Write data
from core
Read data
to core
ARM7TDMI