Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-25
6.16 Coprocessor register transfer, load from coprocessor
The busy-wait cycles are similar to those described in Coprocessor data transfer from
memory to coprocessor on page 6-21, but the transfer is limited to one word, and the
ARM7TDMI core puts the data into the destination register in the third cycle. The third
cycle can be merged with the next prefetch cycle into one memory N-cycle as with all
processor register load instructions.
The cycle timings are listed in Table 6-19 where:
• b represents the busy cycles.
Note
Coprocessor register transfer operations are not available in Thumb state.
Table 6-19 Coprocessor register transfer, load from coprocessor
Cycle Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB
ready 1 pc+8 2 0 (pc+8) 1 1 0 0 0 0
2 pc+12 2 0 CPdata 1 0 1 1 1 1
3 pc+12 2 0 - 0 1 1 1 - -
-pc+12
not ready 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
2pc+820- 1 01 001
•pc+820- 1 01001
bpc+820- 1 11 000
b+1 pc+12 2 0 CPdata 1 0 1 1 1 1
b+2 pc+12 2 0 - 0 1 1 1 - -
pc+12
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