Memory Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 3-7
The possible burst types are listed in Table 3-2.
All accesses in a burst are of the same data width, direction, and protection type. For
more details, see Addressing signals on page 3-11.
Memory systems can often respond faster to a sequential access and can require a
shorter access time compared to a nonsequential access. An example of a burst access
is shown in Figure 3-3.
Figure 3-3 Sequential access cycles
3.3.3 Internal cycles
During an internal cycle, the ARM7TDMI processor does not require a memory access,
as an internal function is being performed, and no useful prefetching can be performed
at the same time.
Table 3-2 Burst types
Burst type Address increment Cause
Word read 4 bytes ARM7TDMIcore code fetches, or LDM instruction
Word write 4 bytes STM instruction
Halfword read 2 bytes Thumb code fetches
aa+4a+8
MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
N-cycle S-cycle S-cycle
a+12
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