ARM ARM7TDMI User Manual

Programmer’s Model
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 2-15
Mode bits
Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all
combinations of the mode bits define a valid processor mode, so take care to use only
the bit combinations shown.
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
2.7.3 Reserved bits
The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag
or control bits, make sure that these reserved bits are not altered. Also, make sure that
your program does not rely on reserved bits containing specific values because future
processors might have these bits set to 1 or 0.
Table 2-2 PSR mode bit values
M[4:0] Mode Visible Thumb-state registers Visible ARM-state registers
10000 User r0–r7, SP, LR, PC, CPSR r0–r14, PC, CPSR
10001 FIQ r0–r7, SP_fiq, LR_fiq, PC, CPSR,
SPSR_fiq
r0–r7, r8_fiq–r14_fiq, PC, CPSR,
SPSR_fiq
10010 IRQ r0–r7, SP_irq, LR_irq, PC, CPSR,
SPSR_irq
r0–r12, r13_irq, r14_irq, PC, CPSR,
SPSR_irq
10011 Supervisor r0–r7, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
10111 Abort r0–r7, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
11011 Undefined r0–r7, SP_und, LR_und, PC, CPSR,
SPSR_und
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
11111 System r0–r7, SP, LR, PC, CPSR r0–r14, PC, CPSR

ARM ARM7TDMI Specifications

General

Data Width	32-bit
Cores	1
MIPS per MHz	0.9
On-chip Debug	Yes
Instruction Set	ARM
Pipeline Stages	3
Operating Voltage	Implementation dependent
Manufacturing Process	Implementation dependent