ARM ARM7TDMI - Page 60

Programmer’s Model
2-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
All instructions can execute conditionally in ARM state. In Thumb state, only the
Branch instruction can be executed conditionally. For more information about
conditional execution, see the ARM Architecture Reference Manual.
2.7.2 Control bits
The bottom eight bits of a PSR are known collectively as the control bits. They are the:
• interrupt disable bits
• T bit
• mode bits.
The control bits change when an exception occurs. When the processor is operating in
a privileged mode, software can manipulate these bits.
Interrupt disable bits
The I and F bits are the interrupt disable bits:
• when the I bit is set, IRQ interrupts are disabled
• when the F bit is set, FIQ interrupts are disabled.
T bit
The T bit reflects the operating state:
• when the T bit is set, the processor is executing in Thumb state
• when the T bit is clear, the processor executing in ARM state.
The operating state is reflected on the external signal TBIT.
Caution
Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If
you do this, the processor enters an unpredictable state.