ARM ARM7TDMI - Table 2-4 Exception Vectors; Undefined Instruction

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Programmer’s Model

2.8.7 Software interrupt instruction

The Software Interrupt instruction (SWI) is used to enter Supervisor mode, usually to

request a particular supervisor function. The SWI handler reads the opcode to extract

the SWI function number.

A SWI handler returns by executing the following irrespective of the processor

operating state:

MOVS PC, R14_svc

This action restores the PC and CPSR, and returns to the instruction following the SWI.

2.8.8 Undefined instruction

When the ARM7TDMI processor encounters an instruction that neither it, nor any

coprocessor in the system can handle, the ARM7TDMI core takes the undefined

instruction trap. Software can use this mechanism to extend the ARM instruction set by

emulating undefined coprocessor instructions.

After emulating the failed instruction, the trap handler executes the following

irrespective of the processor operating state:

MOVS PC,R14_und

This action restores the CPSR and returns to the next instruction after the undefined

instruction.

For more information about undefined instructions, see the ARM Architecture Reference

Manual.

2.8.9 Exception vectors

Table 2-4 lists the exception vector addresses. In this table, I and F represent the

previous value of the IRQ and FIQ interrupt disable bits respectively in the CPSR.

Table 2-4 Exception vectors

Address Exception Mode on entry I state on entry F state on entry

0x00000000

Reset Supervisor Set Set

0x00000004

Undefined instruction Undefined Set Unchanged

0x00000008

Software interrupt Supervisor Set Unchanged

0x0000000C

Prefetch Abort Abort Set Unchanged

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