ARM ARM7TDMI - Figure 1-3 ARM7 TDMI Main Processor Logic

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Introduction

Figure 1-3 ARM7TDMI main processor logic

Scan control

Instruction

decoder and

logic control

Instruction pipeline

Read data register

Thumb instruction controller

Write data register

nENOUT

DBE

nENIN

B bus

32-bit ALU

Barrel shifter

32 x 8

Multiplier

D[31:0]

DBGRQI

BREAKPTI

DBGACK

ECLK

nEXEC

ISYNC

BL[3:0]

APE

MCLK

nWAIT

nRW

MAS[1:0]

nIRQ

nFIQ

nRESET

ABORT

nTRANS

nMREQ

nOPC

SEQ

LOCK

nCPI

CPA

CPB

nM[4:0]

TBE

TBIT

HIGHZ

ALU bus

(31 x 32-bit registers)

(6 status registers)

A bus

Address

incrementer

Address register

PC bus

A[31:0]

ALE ABE

Incrementer bus

INSTRVALID

Main Page

Preface16
Chapter 1 Introduction22
Chapter 2 Programmer's Model48
Chapter 3 Memory Interface72
Chapter 4 Coprocessor Interface104
Chapter 5 Debug Interface122
Chapter 6 Instruction Cycle Timings145
Chapter 7 Ac and DC Parameters173
Appendix A Signal and Transistor Descriptions200
Appendix B Debug in Depth211
Appendix C271
- Differences between Rev 3A and Rev271
Appendix C Differences between Rev 3A and Rev272
- Summary of Differences between Rev 3A and Rev 4272
- Detailed Descriptions of Differences between Rev 3A and Rev 4273
Glossary277

ARM ARM7TDMI - Figure 1-3 ARM7 TDMI Main Processor Logic

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