Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-3
6.1 About the instruction cycle timing tables
In the following tables:
• nMREQ and SEQ, are pipelined up to one cycle ahead of the cycle to which they
apply. They are shown in the cycle in which they appear and indicate the next
cycle type.
• The address, MAS[1:0], nRW, nOPC, nTRANS, and TBIT signals, that appear
up to half a cycle ahead, are shown in the cycle to which they apply. The address
is incremented to prefetch instructions in most cases. Because the instruction
width is four bytes in ARM state and two bytes in Thumb state, the increment
varies accordingly.
• The letter L is used to indicate instruction length:
— four bytes in ARM state
— two bytes in Thumb state.
• The letter i is used to indicate the width of the instruction fetch output by
MAS[1:0]:
— i=2 in ARM state represents word accesses
— i=1 in Thumb state represents halfword accesses.
• Terms placed inside brackets represent the contents of an address.
• The • symbol indicates zero or more cycles.
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