ARM ARM7TDMI - Coprocessor Data Transfer from Coprocessor to Memory

Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-23
6.15 Coprocessor data transfer from coprocessor to memory
The ARM7TDMI processor controls these instructions in the same way as for memory
to coprocessor transfers, with the exception that the nRW line is inverted during the
transfer cycle.
The cycle timings are listed in Table 6-18 where:
• b represents the busy cycles
• n represents the number of registers.
Table 6-18 coprocessor data transfer instruction cycle operations
CP
register
status
Cycle Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB
Single 1 pc+8 2 0 (pc+8) 0 0 0 0 0 0
register 2 alu 2 1 CPdata 0 0 1 1 1 1
ready - pc+12 - - - - - - - - -
Single 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
register 2 pc+8 2 0 - 1 0 1 0 0 1
not ready • pc+8 2 0 - 1 0 1 0 0 1
bpc+820- 0 01 000
b+1 alu 2 1 CPdata 0 0 1 1 1 1
pc+12
n registers 1 pc+8 2 0 (pc+8) 0 0 0 0 0 0
(n>1) 2 alu 2 1 CPdata 0 1 1 1 0 0
ready • alu+• 2 1 CPdata 0 1 1 1 0 0
n alu+• 2 1 CPdata 0 1 1 1 0 0
n+1 alu+• 2 1 CPdata 0 0 1 1 1 1
pc+12
n registers 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
(n>1) 2 pc+8 2 0 - 1 0 1 0 0 1
not ready • pc+8 2 0 - 1 0 1 0 0 1