ARM ARM7TDMI - Page 164

Instruction Cycle Timings
6-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Note
Coprocessor data transfer operations are not available in Thumb state.
n registers 1 pc+8 2 0 (pc+8) 1 0 0 0 0 1
(n>1) 2 pc+8 2 0 - 1 0 1 0 0 1
not ready • pc+8 2 0 - 1 0 1 0 0 1
bpc+820-0 01000
b+1 alu 2 0 (alu) 0 1 1 1 0 0
•alu+• 0(alu+•)0 11100
n+b alu+• 2 0 (alu+•) 0 1 1 1 0 0
n+b+1 alu+• 2 0 (alu+•) 0 0 1 1 1 1
pc+12
Table 6-17 Coprocessor data transfer instruction cycle operations (continued)
CP
register
status
Cycles Address
MA
S
[1:0]
nRW Data nMREQ SEQ nOPC nCPI CPA CPB