ARM ARM7TDMI User Manual

Instruction Cycle Timings
6-20 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
6.13 Coprocessor data operation
A coprocessor data operation is a request from the core for the coprocessor to initiate
some action. The action does not have to be completed for some time, but the
coprocessor must commit to doing it before driving CPB LOW.
If the coprocessor is not capable of performing the requested task, it must leave CPA
and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA
LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes
LOW.
The cycle timings are listed in Table 6-16 where:
• b represents the busy cycles.
Note
Coprocessor data operations are not available in Thumb state.
Table 6-16 Coprocessor data operation instruction cycle operations
CP
status
Cycle Address nRW
MA
S
[1:0]
Data nMREQ SEQ nOPC nCPI CPA CPB
ready 1 pc+8 0 2 (pc+8) 0 0 0 0 0 0
pc+12
not ready 1 pc+8 0 2 (pc+8) 1 0 0 0 0 1
2pc+802- 1 01001
•pc+802- 1 01001
bpc+802- 0 01 000
pc+12

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English