Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-3
B.1 Scan chains and the JTAG interface
Three JTAG-style scan chains within the ARM7TDMI core enable debugging and
configuration of EmbeddedICE-RT logic.
Support is also provided for an optional fourth scan chain. This is intended to be used
for an external boundary-scan chain around the pads of a packaged device. The control
signals provided for this scan chain are described in Scan chain 3 on page B-20. Two
additional scan chains exist (numbered four and eight), but these are reserved for ARM
use only.
See Table B-2 on page B-16 for a summary of scan chain number allocation.
The following sections describe:
• Scan chain implementation
• TAP state machine on page B-5.
B.1.1 Scan chain implementation
A JTAG-style Test Access Port (TAP) controller controls the scan chains. For further
details of the JTAG specification, see IEEE Standard 1149.1 - 1990 Standard Test
Access Port and Boundary-Scan Architecture.
The scan chains are shown in Figure B-1 on page B-4.
Scan chains 0, 1, and 2 are described in the following sections:
• Scan chain 0 on page B-4
• Scan chain 1 on page B-4
• Scan chain 2 on page B-5.
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