ARM ARM7TDMI - Table 6-10 MAS[1:0] Signal Encoding

Instruction Cycle Timings
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 6-13
Note
Operations where the destination is the PC are not available in Thumb state.
4pc’ 2 0(pc’)0 10c
5 pc’+4 2 0 (pc’+4) 0 1 0 c
pc’+8
Table 6-9 Load register instruction cycle operations (continued)
Operation type Cycle Address MAS[1:0] nRW Data nMREQ SEQ nOPC nTRANS
Table 6-10 MAS[1:0] signal encoding
Bit [1] Bit [0] Data size
00byte
01halfword
10word
1 1 reserved