ARM ARM7TDMI - Table 7-2 ABE Address Control Timing Parameters; Figure 7-2 ABE Address Control; Figure 7-3 Bidirectional Data Write Cycle

AC and DC Parameters
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-5
Figure 7-2 ABE address control
The timing parameters used in Figure 7-2 are listed in Table 7-2.
Figure 7-3 Bidirectional data write cycle
Note
In Figure 7-3 DBE is HIGH and nENIN is LOW during the cycle shown.
MCLK
ABE
A[31:0]
nRW
LOCK
nOPC
nTRANS
MAS[1:0]
T
abz
T
abe
Table 7-2 ABE address control timing parameters
Symbol Parameter Parameter type
T
abe
Address bus enable time Maximum
T
abz
Address bus disable time Maximum
MCLK
nENOUT
D[31:0]
T
nen
T
dout
T
nenh
T
doh