ARM ARM7TDMI - Table 7-16 TCK and ECLK Timing Parameters; Table 7-17 MCLK Timing Parameters; Figure 7-17 MCLK Timing

AC and DC Parameters
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 7-15
The timing parameter used in Figure 7-16 on page 7-14 is listed in Table 7-16.
Figure 7-17 MCLK timing
Note
In Figure 7-17, the core is not clocked by the HIGH phase of MCLK when nWAIT is
LOW. During the cycles shown, nMREQ and SEQ change once, during the first LOW
phase of MCLK, and A[31:0] change once, during the second HIGH phase of MCLK.
Phase 2 is shown for reference. This is the internal clock from which the core times all
its activity. This signal is included to show how the HIGH phase of the external MCLK
has been removed from the internal core clock.
The timing parameters used in Figure 7-17 are listed in Table 7-17.
Table 7-16 TCK and ECLK timing parameters
Symbol Parameter Parameter type
T
ctdel
TCK to ECLK delay Maximum
T
mckh
T
mckl
T
ws
T
wh
T
msd
T
addr
MCLK
nWAIT
nMREQ
SEQ
ECLK
A[31:0]
Table 7-17 MCLK timing parameters
Symbol Parameter Parameter type
T
addr
MCLKr to address valid Maximum
T
mckh
MCLK HIGH time Minimum
T
mckl
MCLK LOW time Minimum