Debug in Depth
B-22 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
B.7 The ARM7TDMI core clocks
The ARM7TDMI core has two clocks:
• the memory clock, MCLK
• an internally TCK generated clock, DCLK (see Clocks on page 5-3).
During normal operation, the core is clocked by MCLK and internal logic holds DCLK
LOW.
When the ARM7TDMI core is in debug state, the core is clocked by DCLK under
control of the TAP state machine and MCLK can free-run. The selected clock is output
on the signal ECLK for use by the external system.
Note
nWAIT must be HIGH in debug state.
In monitor mode, the core continues to be clocked by MCLK, and DCLK is not used.
B.7.1 Clock switch during debug
When the ARM7TDMI core enters halt mode, it must switch from MCLK to DCLK.
This is handled automatically by logic in the ARM7TDMI core. On entry to debug state,
the core asserts DBGACK in the HIGH phase of MCLK. The switch between the two
clocks occurs on the next falling edge of MCLK. This is shown in Figure B-5.
Figure B-5 Clock switching on entry to debug state
The ARM7TDMI core is forced to use DCLK as the primary clock until debugging is
complete. On exit from debug, the core must be synchronized back to MCLK as
follows:
1. The final instruction of the debug sequence must be shifted into the data bus scan
chain and clocked in by asserting DCLK.
MCLK
DBGACK
DCLK
ECLK
Multiplexer
switching point
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