ARM ARM7TDMI - Page 233

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-23
2. RESTART must be clocked into the TAP instruction register.
The ARM7TDMI core automatically resynchronizes to MCLK and starts fetching
instructions from memory at MCLK speed.
See Exit from debug state on page B-27.
Note
In monitor mode, the core continues to be clocked by MCLK, and DCLK is not used.
B.7.2 Clock switch during test
When under serial test conditions, that is when test patterns are being applied to the
ARM7TM core through the JTAG interface, the ARM7TDMI core must be clocked
using DCLK. Entry into test is less automatic than debug and some care must be taken.
On the way into test, MCLK must be held LOW. The TAP controller can now be used
to serially test the ARM7TDMI core. If scan chain 0 and INTEST are selected, DCLK
is generated while the state machine is in the RUN-TEST-IDLE state. During EXTEST,
DCLK is not generated.
On exit from test, RESTART must be selected as the TAP controller instruction. When
this is done, MCLK can be enabled to resume.
Note
After INTEST testing, you must ensure that the core is in a sensible state before
switching back to standard operating mode. The safest ways to do this are as follows:
• select RESTART and then cause a system reset
•insert
MOV PC, #0 into the instruction pipeline.