ARM ARM7TDMI - Embeddedice-RT Timing

Debug in Depth
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. B-59
B.19 EmbeddedICE-RT timing
EmbeddedICE-RT samples the EXTERN1 and EXTERN0 inputs on the falling edge
of ECLK. Sufficient set-up and hold time must therefore be enabled for these signals.
See Chapter 7 AC and DC Parameters for details of the required setup and hold times
for these signals.