ARM ARM7TDMI - Table 7-9 Configuration Pin Timing Parameters; Table 7-10 Coprocessor Timing Parameters; Figure 7-10 Coprocessor Timing

AC and DC Parameters
7-10 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
The timing parameters used in Figure 7-9 on page 7-9 are listed in Table 7-9.
Figure 7-10 Coprocessor timing
Note
In Figure 7-10, usually nMREQ and SEQ become valid T
msd
after the falling edge of
MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the
instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ
depends on T
cpms
. Most systems can generate CPA and CPB during the previous phase
2, and so the timing of nMREQ and SEQ is always T
msd
.
The timing parameters used in Figure 7-10 are listed in Table 7-10.
Table 7-9 Configuration pin timing parameters
Symbol Parameter Parameter type
T
cth
Configurations hold time Minimum
T
cts
Configuration setup time Minimum
T
cps
T
cpi
Phase 2
T
cph
T
cpih
MCLK
nCPI
CPA
CPB
nMREQ
SEQ
T
cpms
Phase 1
Table 7-10 Coprocessor timing parameters
Symbol Parameter Parameter type
T
cph
CPA,CPB hold time from MCLKrMinimum
T
cpi
MCLKf to nCPI valid Maximum
T
cpih
nCPI hold time from MCLKfMinimum
T
cpms
CPA, CPB to nMREQ, SEQ Maximum
T
cps
CPA, CPB setup to MCLKrMinimum