ARM ARM7TDMI User Manual

AC and DC Parameters
7-2 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
7.1 Timing diagrams
The AC timing diagrams provided in this section are as follows.
• General timings on page 7-3
• ABE address control on page 7-5
• Bidirectional data write cycle on page 7-5
• Bidirectional data read cycle on page 7-6
• Data bus control on page 7-7
• Output 3-state time on page 7-8
• Unidirectional data write cycle on page 7-8
• Unidirectional data read cycle on page 7-9
• Configuration pin timing on page 7-9
• Coprocessor timing on page 7-10
• Exception timing on page 7-11
• Synchronous interrupt timing on page 7-12
• Debug timing on page 7-12
• DCC output timing on page 7-13
• Breakpoint timing on page 7-14
• TCK and ECLK relationship on page 7-14
• MCLK timing on page 7-15
• Scan general timing on page 7-16
• Reset period timing on page 7-17
• Output enable and disable times due to HIGHZ TAP instruction on page 7-17
• Output enable and disable times due to data scanning on page 7-18.
• ALE address control on page 7-18
• APE address control on page 7-19.
Note
Each diagram is provided with a table that describes the timing parameters. In the
tables:
• the letter f at the end of a signal name indicates the falling edge
• the letter r at the end of a signal name indicates the rising edge.

ARM ARM7TDMI Specifications

General

Brand	ARM
Model	ARM7TDMI
Category	Computer Hardware
Language	English