ARM ARM7TDMI - Figure 4-4 Coprocessor Load Sequence

Coprocessor Interface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 4-11
Figure 4-4 Coprocessor load sequence
ADD SUB LDC n=4 TST SUB
ADD SUB LDC TST SUB
ADD SUB LDC TST SUB
MCLK
Fetch stage
Decode
stage
Execute
stage
nCPI
CPA
CPB
D[31:0]
CP Data Instr fetch
Instr fetch
(SUB)
CP Data CP Data CP Data
Instr fetch
(ADD)
Instr fetch
(LDC)
Instr fetch
(TST)
Instr fetch
(SUB)