ARM ARM7TDMI - Figure 4-1 Coprocessor Busy-Wait Sequence

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Coprocessor Interface

Figure 4-1 Coprocessor busy-wait sequence

CPA and CPB are ignored by the ARM7TDMI processor when it does not have a

undefined or coprocessor instruction in the Execute stage of the pipeline.

A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.

4.4.4 Consequences of busy-waiting

A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs

and the appropriate bit is clear in the CSPR, then the ARM7TDMI processor abandons

the coprocessor instruction, and signals this by taking nCPI HIGH. A coprocessor that

is capable of busy-waiting must monitor nCPI to detect this condition. When the

ARM7TDMI core abandons a coprocessor instruction, the coprocessor also abandons

the instruction, and continues tracking the ARM7TDMI processor pipeline.

ADD SUB CDP TST SUB

Instr fetch

(ADD)

Instr fetch

(CDP)

Instr fetch

(TST)

Instr fetch

(SUB)

Instr fetch Instr fetch

Instr fetch

(SUB)

MCLK

Fetch stage

Decode stage

Execute

stage

nCPI

CPA

CPB

D[31:0]

Coprocessor

busy waiting

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